1. Field of the Invention
The present invention relates to an FLL (Frequency locked loop) circuit, a PLL (Phase locked loop) circuit, and a wireless communication circuit, which are applied in a frequency synthesizer, a frequency modulation circuit, and the like; and more specifically, relates to an FLL circuit, a PLL circuit, and a wireless communication device that uses the FLL circuit and/or the PLL circuit, all having a capability of configuring a loop bandwidth to a desired bandwidth in a short period of time.
2. Description of the Background Art
FIG. 15 is a block diagram showing a configuration of a conventional FLL circuit 500 that is used as a frequency synthesizer. In FIG. 15 the conventional FLL circuit 500 includes: a frequency error detector 501; a loop filter 502; a VCO (Voltage Controlled Oscillator) 503; and an FDC (Frequency Digital Converter) 504. Within the FLL circuit 500, a control voltage that is in accordance with an input signal is supplied to the VCO 503 via the frequency error detector 501 and the loop filter 502. The VCO 503 generates an output signal having a frequency that is in accordance with the control voltage. The FDC 504 detects the frequency of the output signal of the VCO 503, converts the frequency into a digital signal, and outputs the resulting digital signal to the frequency error detector 501. The frequency error detector 501 compares the input signal and the output signal of the FDC 504, and detects an error between a frequency of the input signal and the frequency of the output signal of the VCO 503. The conventional FLL circuit 500 operates so as to reduce an output from the frequency error detector 501 to zero; which means, to equalize the frequency of the input signal and the frequency of the output signal of the VCO 503. A conventional FLL circuit controls the frequency of the output signal of the VCO 503 by means of a feedback control that uses a closed-loop as described above. Descriptions of the PLL circuit are omitted, since the PLL circuit has a configuration that is largely similar to that of the FLL circuit 500.
However, with the conventional FLL/PLL circuit 500, when a sensitivity of the VCO 503 fluctuates due to a process variation and a temperature fluctuation, a loop bandwidth will also fluctuate as a result. If the loop bandwidth fluctuates and veers away from an optimum value, various problems, such as degradation of output frequency precision and requirement of longer time until the FLL/PLL circuit locks up, arise due to influences such as a noise within a loop band, nonlinearity of the VCO 503, and the like.
In order to solve this problem, for example, a PLL circuit, which has a capability of configuring a loop bandwidth to a desired bandwidth even when the sensitivity of the VCO fluctuates, is disclosed in Japanese National Phase PCT Laid-Open Publication No. 2007-507985 (hereinafter, described as patent document 1). FIG. 16 is a block diagram showing one example of a conventional PLL circuit 510 disclosed in patent document 1. In the conventional PLL circuit 510, a Kv measuring circuit 514 measures control voltages V1 and V2 of a VCO 513 when an output signal of the VCO 513 is locked at frequencies f1 and f2, and then measures a gain Kv of the VCO 513 by using formula 1. The Kv controller 515 controls a level of a charge-pump current that is outputted by a charge pump 511, such that a product, obtained by multiplying the measured gain Kv of the VCO 513 by the charge-pump current, becomes constant.Kv=(f2−f1)/(V2−V1)  (formula 1)
However, the conventional PLL circuit 510 disclosed in patent document 1 has the following problem. It is necessary for the conventional PLL circuit 510 to lock up output frequencies f1 and f2 of the VCO 513 by means of a closed-loop control when measuring control voltages V1 and V2 of the VCO 513. Since output frequencies are converged to a desired frequency by utilizing an error of the VCO 513 output signal as a feedback, there is a limit in shortening a lock up time. Furthermore, in order to obtain a measurement precision that is sufficient, it is necessary to wait for a sufficient period of time after locking the output frequencies f1 and f2 of the VCO 513 before measuring the control voltages V1 and V2; thus ensuring measurement precision also requires time. Therefore, the conventional PLL circuit 510 disclosed in patent document 1 has a problem, which is the difficulty in configuring the loop bandwidth to a desired bandwidth in a short period of time.